The following documents are incorporated by reference herein:
1. M. Bruel, “A new silicon on insulator material technology”, Electron. Lett. 31, 1201-1202 (1995).
2. U.S. Pat. No. 5,374,564 M. Bruel
3. M. Wanlass et al., “Monolithic, Ultra-Thin GaInP/GaAs/GaInAsTandem Solar Cells,” NREL/PR-520-39852, Presented at the 2006 IEEE 4th World Conference on Photovoltaic Energy Conversion (WCPEC-4) held May 7-12, 2006 in Waikoloa, Hi.
4. F. J. Kub et al., “Ultra-Thin Silicon Complaint Layers for Infrared Materials,” Naval Research Laboratory/OMB 0704-0188, 1998.
5. M. S. Goorsky et al., “Engineered Layer Transfer Substrates for Heterogeneous Integration of III-V Compound Semiconductors,” 2008 The International Conference on Compound Semiconductor Manufacturing Technology.
6. R. Brendel, “Crystalline thin-film silicon solar cells from layer-transfer processes: a review,” Proc. 10th Workshop on Crystalline Silicon Solar Cell Materials and Processes, Aug. 13-16, 2000, Copper Mountain, USA.
7. U.S. Pat. No. 7,855,101 B. K. Furman et al.
8. M. M. A. J. Voncken et al., “Etching AlAs with HF for Epitaxial Lift-Off Applications,” Journal of the Electrochemical Society, 151, no 5 (2004): G347-G352.
9. N. M. Jokerst et al., “The Heterogeneous Integration of Optical Interconnections Into Integrated Microsystems,” IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, 9, no. 2, MARCH/APRIL 2003.
10X. Y. Lee et al., “Thin Film GaAs Solar Cells on Glass Substrates by Epitaxial Liftoff,” National renewable energy laboratory and sandia national laboratories photovoltaics program review meeting. AIP Conference Proceedings, 394, (1997): 719-727.
11. M. J. Archer et al., “Materials Processes for Ultrahigh Efficiency Lattice Mismatched Multijunction Solar Cells,” SPIE Optics+Photonics (2007): 6649-14.
12. U.S. Pat. No. 7,935,612 S. Bedell et al.
13. U.S. Pat. No. 7,905,197 E. T -S. Pan
14. U.S. Pat. No, 8,193,078 E. T -S. Pan
15. U. Gosele et al., “Fundamental Issues in Wafer Bonding,” JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY A, 17(4), July/August 1999.
Prior art layer transfer methods typically separate grown epitaxy layer(s) or finished device structure from a parent wafer substrate to a daughter substrate. The different types of prior art processes typically practiced as follows:
1) Commonly known as Ion Cut or Smart Cut—cleave fine monocrystalline layers by inducing, through ion implantation to create a mechanically weak zone below the surface of the donor wafer. The implanted wafer is then bonded to a handle wafer and the obtained pair is subjected to thermal annealing to produce voids and extended internal surfaces in terms of pressurized microcracks parallel to the bonding interface. This leads to the splitting and transfer of a thin monocrystalline layer with a thickness roughly equivalent to the implantation depth (see references #1, #2 above).
2) Deposit a backside contact and back surface reflector atop an inverted tandem structure which is grown on an etch stop layer over a first substrate. Mount the inverted tandem structure upside down on a second substrate. Remove the etch stop layer and thus the first substrate. Complete frontside processing of the tandem structure on the second substrate (see reference #3).
3) Deposit some layers on a first substrate, and other layers on a second substrate. Polish and bond the two-layered substrates by annealing. Detach the second substrate by a hydrogen implantation, leaving the desired layer combination on the first substrate (see references #4, #5).
4) Prepare a surface layer (surface conditioning) on a silicon substrate. Grow a device layer on the surface treated layer. Attach a carrier to the device layer. Remove the surface layer and the silicon substrate (see reference #6).
5Build a semiconductor device layer on a first substrate. Provide a set of first functional elements to connect in the semiconductor device layer. Attach a carrier substrate on top of the first functional elements. Remove the first substrate to expose the bottom side of the semiconductor device layer producing a first intermediate structure. Build a set of second functional elements on a foundation substrate to produce a second intermediate structure. Bond the first and the second intermediate structures to form a third intermediate structure. Remove the carrier substrate. Provide input output means on the exposed surface of the first functional elements to form the integrated device structure (see reference #7).
6) An epitaxial lift-off process allows the separation of a thin layer of compound semiconductor material from a substrate by strain-accelerated selective etching of an intermediate or sacrificial layer. Other means of removing the sacrificial layer in ELO include laser-assisted lift-off, ion bombardment (see reference #8).
7) Fabricate devices on an etch stop layer (epitaxial surface) grown on a substrate. Mesa etch to etch stop layer and pattern separate devices. Remove the substrate using selective wet etching. Bond the device onto a host substrate using a transfer diaphragm (see reference #9).
8) Wax the top of a device. Lift-off in a selective chemical etch of a sacrificial layer and remove the substrate. Attach the lift-off device to a glass substrate. Remove wax in chemical removal step (see reference #10).
9) Implant a device template substrate. Activate and clean the surface of the device template substrate and the handle substrate. Initiate a bond at room temperature. Apply uniform pressure and heat to the stacked wafers to strengthen the bond and initiate exfoliation (see reference #11).
10) Form an upper silicon (Si) layer over a boron-doped SiGe layer. Hydrogenate the boron-doped SiGe layer by hydrogen plasma without ion implantation. Bond the upper Si layer to an alternate substrate and propagate a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate (see reference #12).
Other improved processes are shown in references #13 and #14 above to the instant inventor. There is still a need for further improvements in this field.